/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_ROM_REGISTERS_H__
#define __HW_ROM_REGISTERS_H__

#include "regs.h"

/*
 * MKL46Z4 ROM
 *
 * System ROM
 *
 * Registers defined in this header file:
 * - HW_ROM_ENTRYn - Entry
 * - HW_ROM_TABLEMARK - End of Table Marker Register
 * - HW_ROM_SYSACCESS - System Access Register
 * - HW_ROM_PERIPHID4 - Peripheral ID Register
 * - HW_ROM_PERIPHID5 - Peripheral ID Register
 * - HW_ROM_PERIPHID6 - Peripheral ID Register
 * - HW_ROM_PERIPHID7 - Peripheral ID Register
 * - HW_ROM_PERIPHID0 - Peripheral ID Register
 * - HW_ROM_PERIPHID1 - Peripheral ID Register
 * - HW_ROM_PERIPHID2 - Peripheral ID Register
 * - HW_ROM_PERIPHID3 - Peripheral ID Register
 * - HW_ROM_COMPIDn - Component ID Register
 *
 * - hw_rom_t - Struct containing all module registers.
 */

//! @name Module base addresses
//@{
#ifndef REGS_ROM_BASE
#define HW_ROM_INSTANCE_COUNT (1U) //!< Number of instances of the ROM module.
#define REGS_ROM_BASE (0xF0002000U) //!< Base address for ROM.
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_ENTRYn - Entry
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_ENTRYn - Entry (RO)
 *
 * Reset value: 0x00000000U
 *
 * The System ROM Table begins with "n" relative 32-bit addresses, one for each
 * debug component present in the device and terminating with an all-zero value
 * signaling the end of the table at the "n+1"-th value. It is hardwired to
 * specific values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_entryn
{
    uint32_t U;
    struct _hw_rom_entryn_bitfields
    {
        uint32_t ENTRY : 32;           //!< [31:0] ENTRY
    } B;
} hw_rom_entryn_t;
#endif

/*!
 * @name Constants and macros for entire ROM_ENTRYn register
 */
//@{
#define HW_ROM_ENTRYn_COUNT (3U)

#define HW_ROM_ENTRYn_ADDR(n)    (REGS_ROM_BASE + 0x0U + (0x4U * n))

#ifndef __LANGUAGE_ASM__
#define HW_ROM_ENTRYn(n)         (*(__I hw_rom_entryn_t *) HW_ROM_ENTRYn_ADDR(n))
#define HW_ROM_ENTRYn_RD(n)      (HW_ROM_ENTRYn(n).U)
#endif
//@}

/*
 * Constants & macros for individual ROM_ENTRYn bitfields
 */

/*!
 * @name Register ROM_ENTRYn, field ENTRY[31:0] (RO)
 *
 * Entry 0 (MTB) is hardwired to 0xFFFF_E003; Entry 1 (MTBDWT) to 0xFFFF_F003;
 * Entry 2 (CM0+ ROM Table) to 0xF00F_D003.
 */
//@{
#define BP_ROM_ENTRYn_ENTRY  (0U)          //!< Bit position for ROM_ENTRYn_ENTRY.
#define BM_ROM_ENTRYn_ENTRY  (0xFFFFFFFFU) //!< Bit mask for ROM_ENTRYn_ENTRY.
#define BS_ROM_ENTRYn_ENTRY  (32U)         //!< Bit field size in bits for ROM_ENTRYn_ENTRY.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_ENTRYn_ENTRY field.
#define BR_ROM_ENTRYn_ENTRY(n) (BME_UBFX32(HW_ROM_ENTRYn_ADDR(n), BP_ROM_ENTRYn_ENTRY, BS_ROM_ENTRYn_ENTRY))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_TABLEMARK - End of Table Marker Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_TABLEMARK - End of Table Marker Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * This register indicates end of table marker. It is hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_tablemark
{
    uint32_t U;
    struct _hw_rom_tablemark_bitfields
    {
        uint32_t MARK : 32;            //!< [31:0]
    } B;
} hw_rom_tablemark_t;
#endif

/*!
 * @name Constants and macros for entire ROM_TABLEMARK register
 */
//@{
#define HW_ROM_TABLEMARK_ADDR    (REGS_ROM_BASE + 0xCU)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_TABLEMARK         (*(__I hw_rom_tablemark_t *) HW_ROM_TABLEMARK_ADDR)
#define HW_ROM_TABLEMARK_RD()    (HW_ROM_TABLEMARK.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_TABLEMARK bitfields
 */

/*!
 * @name Register ROM_TABLEMARK, field MARK[31:0] (RO)
 *
 * Hardwired to 0x0000_0000
 */
//@{
#define BP_ROM_TABLEMARK_MARK (0U)         //!< Bit position for ROM_TABLEMARK_MARK.
#define BM_ROM_TABLEMARK_MARK (0xFFFFFFFFU) //!< Bit mask for ROM_TABLEMARK_MARK.
#define BS_ROM_TABLEMARK_MARK (32U)        //!< Bit field size in bits for ROM_TABLEMARK_MARK.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_TABLEMARK_MARK field.
#define BR_ROM_TABLEMARK_MARK (BME_UBFX32(HW_ROM_TABLEMARK_ADDR, BP_ROM_TABLEMARK_MARK, BS_ROM_TABLEMARK_MARK))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_SYSACCESS - System Access Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_SYSACCESS - System Access Register (RO)
 *
 * Reset value: 0x00000001U
 *
 * This register indicates system access. It is hardwired to specific values
 * used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_sysaccess
{
    uint32_t U;
    struct _hw_rom_sysaccess_bitfields
    {
        uint32_t SYSACCESS : 32;       //!< [31:0]
    } B;
} hw_rom_sysaccess_t;
#endif

/*!
 * @name Constants and macros for entire ROM_SYSACCESS register
 */
//@{
#define HW_ROM_SYSACCESS_ADDR    (REGS_ROM_BASE + 0xFCCU)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_SYSACCESS         (*(__I hw_rom_sysaccess_t *) HW_ROM_SYSACCESS_ADDR)
#define HW_ROM_SYSACCESS_RD()    (HW_ROM_SYSACCESS.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_SYSACCESS bitfields
 */

/*!
 * @name Register ROM_SYSACCESS, field SYSACCESS[31:0] (RO)
 *
 * Hardwired to 0x0000_0001
 */
//@{
#define BP_ROM_SYSACCESS_SYSACCESS (0U)    //!< Bit position for ROM_SYSACCESS_SYSACCESS.
#define BM_ROM_SYSACCESS_SYSACCESS (0xFFFFFFFFU) //!< Bit mask for ROM_SYSACCESS_SYSACCESS.
#define BS_ROM_SYSACCESS_SYSACCESS (32U)   //!< Bit field size in bits for ROM_SYSACCESS_SYSACCESS.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_SYSACCESS_SYSACCESS field.
#define BR_ROM_SYSACCESS_SYSACCESS (BME_UBFX32(HW_ROM_SYSACCESS_ADDR, BP_ROM_SYSACCESS_SYSACCESS, BS_ROM_SYSACCESS_SYSACCESS))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID4 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID4 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid4
{
    uint32_t U;
    struct _hw_rom_periphid4_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid4_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID4 register
 */
//@{
#define HW_ROM_PERIPHID4_ADDR    (REGS_ROM_BASE + 0xFD0U)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID4         (*(__I hw_rom_periphid4_t *) HW_ROM_PERIPHID4_ADDR)
#define HW_ROM_PERIPHID4_RD()    (HW_ROM_PERIPHID4.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID4 bitfields
 */

/*!
 * @name Register ROM_PERIPHID4, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID4_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID4_PERIPHID.
#define BM_ROM_PERIPHID4_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID4_PERIPHID.
#define BS_ROM_PERIPHID4_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID4_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID4_PERIPHID field.
#define BR_ROM_PERIPHID4_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID4_ADDR, BP_ROM_PERIPHID4_PERIPHID, BS_ROM_PERIPHID4_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID5 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID5 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid5
{
    uint32_t U;
    struct _hw_rom_periphid5_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid5_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID5 register
 */
//@{
#define HW_ROM_PERIPHID5_ADDR    (REGS_ROM_BASE + 0xFD4U)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID5         (*(__I hw_rom_periphid5_t *) HW_ROM_PERIPHID5_ADDR)
#define HW_ROM_PERIPHID5_RD()    (HW_ROM_PERIPHID5.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID5 bitfields
 */

/*!
 * @name Register ROM_PERIPHID5, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID5_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID5_PERIPHID.
#define BM_ROM_PERIPHID5_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID5_PERIPHID.
#define BS_ROM_PERIPHID5_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID5_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID5_PERIPHID field.
#define BR_ROM_PERIPHID5_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID5_ADDR, BP_ROM_PERIPHID5_PERIPHID, BS_ROM_PERIPHID5_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID6 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID6 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid6
{
    uint32_t U;
    struct _hw_rom_periphid6_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid6_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID6 register
 */
//@{
#define HW_ROM_PERIPHID6_ADDR    (REGS_ROM_BASE + 0xFD8U)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID6         (*(__I hw_rom_periphid6_t *) HW_ROM_PERIPHID6_ADDR)
#define HW_ROM_PERIPHID6_RD()    (HW_ROM_PERIPHID6.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID6 bitfields
 */

/*!
 * @name Register ROM_PERIPHID6, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID6_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID6_PERIPHID.
#define BM_ROM_PERIPHID6_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID6_PERIPHID.
#define BS_ROM_PERIPHID6_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID6_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID6_PERIPHID field.
#define BR_ROM_PERIPHID6_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID6_ADDR, BP_ROM_PERIPHID6_PERIPHID, BS_ROM_PERIPHID6_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID7 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID7 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid7
{
    uint32_t U;
    struct _hw_rom_periphid7_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid7_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID7 register
 */
//@{
#define HW_ROM_PERIPHID7_ADDR    (REGS_ROM_BASE + 0xFDCU)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID7         (*(__I hw_rom_periphid7_t *) HW_ROM_PERIPHID7_ADDR)
#define HW_ROM_PERIPHID7_RD()    (HW_ROM_PERIPHID7.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID7 bitfields
 */

/*!
 * @name Register ROM_PERIPHID7, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID7_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID7_PERIPHID.
#define BM_ROM_PERIPHID7_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID7_PERIPHID.
#define BS_ROM_PERIPHID7_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID7_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID7_PERIPHID field.
#define BR_ROM_PERIPHID7_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID7_ADDR, BP_ROM_PERIPHID7_PERIPHID, BS_ROM_PERIPHID7_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID0 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID0 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid0
{
    uint32_t U;
    struct _hw_rom_periphid0_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid0_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID0 register
 */
//@{
#define HW_ROM_PERIPHID0_ADDR    (REGS_ROM_BASE + 0xFE0U)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID0         (*(__I hw_rom_periphid0_t *) HW_ROM_PERIPHID0_ADDR)
#define HW_ROM_PERIPHID0_RD()    (HW_ROM_PERIPHID0.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID0 bitfields
 */

/*!
 * @name Register ROM_PERIPHID0, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID0_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID0_PERIPHID.
#define BM_ROM_PERIPHID0_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID0_PERIPHID.
#define BS_ROM_PERIPHID0_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID0_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID0_PERIPHID field.
#define BR_ROM_PERIPHID0_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID0_ADDR, BP_ROM_PERIPHID0_PERIPHID, BS_ROM_PERIPHID0_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID1 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID1 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid1
{
    uint32_t U;
    struct _hw_rom_periphid1_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid1_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID1 register
 */
//@{
#define HW_ROM_PERIPHID1_ADDR    (REGS_ROM_BASE + 0xFE4U)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID1         (*(__I hw_rom_periphid1_t *) HW_ROM_PERIPHID1_ADDR)
#define HW_ROM_PERIPHID1_RD()    (HW_ROM_PERIPHID1.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID1 bitfields
 */

/*!
 * @name Register ROM_PERIPHID1, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID1_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID1_PERIPHID.
#define BM_ROM_PERIPHID1_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID1_PERIPHID.
#define BS_ROM_PERIPHID1_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID1_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID1_PERIPHID field.
#define BR_ROM_PERIPHID1_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID1_ADDR, BP_ROM_PERIPHID1_PERIPHID, BS_ROM_PERIPHID1_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID2 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID2 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid2
{
    uint32_t U;
    struct _hw_rom_periphid2_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid2_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID2 register
 */
//@{
#define HW_ROM_PERIPHID2_ADDR    (REGS_ROM_BASE + 0xFE8U)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID2         (*(__I hw_rom_periphid2_t *) HW_ROM_PERIPHID2_ADDR)
#define HW_ROM_PERIPHID2_RD()    (HW_ROM_PERIPHID2.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID2 bitfields
 */

/*!
 * @name Register ROM_PERIPHID2, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID2_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID2_PERIPHID.
#define BM_ROM_PERIPHID2_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID2_PERIPHID.
#define BS_ROM_PERIPHID2_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID2_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID2_PERIPHID field.
#define BR_ROM_PERIPHID2_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID2_ADDR, BP_ROM_PERIPHID2_PERIPHID, BS_ROM_PERIPHID2_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_PERIPHID3 - Peripheral ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_PERIPHID3 - Peripheral ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the peripheral IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_periphid3
{
    uint32_t U;
    struct _hw_rom_periphid3_bitfields
    {
        uint32_t PERIPHID : 32;        //!< [31:0]
    } B;
} hw_rom_periphid3_t;
#endif

/*!
 * @name Constants and macros for entire ROM_PERIPHID3 register
 */
//@{
#define HW_ROM_PERIPHID3_ADDR    (REGS_ROM_BASE + 0xFECU)

#ifndef __LANGUAGE_ASM__
#define HW_ROM_PERIPHID3         (*(__I hw_rom_periphid3_t *) HW_ROM_PERIPHID3_ADDR)
#define HW_ROM_PERIPHID3_RD()    (HW_ROM_PERIPHID3.U)
#endif
//@}

/*
 * Constants & macros for individual ROM_PERIPHID3 bitfields
 */

/*!
 * @name Register ROM_PERIPHID3, field PERIPHID[31:0] (RO)
 *
 * Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the
 * others to 0x0000_0000.
 */
//@{
#define BP_ROM_PERIPHID3_PERIPHID (0U)     //!< Bit position for ROM_PERIPHID3_PERIPHID.
#define BM_ROM_PERIPHID3_PERIPHID (0xFFFFFFFFU) //!< Bit mask for ROM_PERIPHID3_PERIPHID.
#define BS_ROM_PERIPHID3_PERIPHID (32U)    //!< Bit field size in bits for ROM_PERIPHID3_PERIPHID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_PERIPHID3_PERIPHID field.
#define BR_ROM_PERIPHID3_PERIPHID (BME_UBFX32(HW_ROM_PERIPHID3_ADDR, BP_ROM_PERIPHID3_PERIPHID, BS_ROM_PERIPHID3_PERIPHID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// HW_ROM_COMPIDn - Component ID Register
//-------------------------------------------------------------------------------------------

#ifndef __LANGUAGE_ASM__
/*!
 * @brief HW_ROM_COMPIDn - Component ID Register (RO)
 *
 * Reset value: 0x00000000U
 *
 * These registers indicate the component IDs. They are hardwired to specific
 * values used during the auto-discovery process by an external debug agent.
 */
typedef union _hw_rom_compidn
{
    uint32_t U;
    struct _hw_rom_compidn_bitfields
    {
        uint32_t COMPID : 32;          //!< [31:0] Component ID
    } B;
} hw_rom_compidn_t;
#endif

/*!
 * @name Constants and macros for entire ROM_COMPIDn register
 */
//@{
#define HW_ROM_COMPIDn_COUNT (4U)

#define HW_ROM_COMPIDn_ADDR(n)   (REGS_ROM_BASE + 0xFF0U + (0x4U * n))

#ifndef __LANGUAGE_ASM__
#define HW_ROM_COMPIDn(n)        (*(__I hw_rom_compidn_t *) HW_ROM_COMPIDn_ADDR(n))
#define HW_ROM_COMPIDn_RD(n)     (HW_ROM_COMPIDn(n).U)
#endif
//@}

/*
 * Constants & macros for individual ROM_COMPIDn bitfields
 */

/*!
 * @name Register ROM_COMPIDn, field COMPID[31:0] (RO)
 *
 * Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to
 * 0x0000_0005; ID3 to 0x0000_00B1.
 */
//@{
#define BP_ROM_COMPIDn_COMPID (0U)         //!< Bit position for ROM_COMPIDn_COMPID.
#define BM_ROM_COMPIDn_COMPID (0xFFFFFFFFU) //!< Bit mask for ROM_COMPIDn_COMPID.
#define BS_ROM_COMPIDn_COMPID (32U)        //!< Bit field size in bits for ROM_COMPIDn_COMPID.

#ifndef __LANGUAGE_ASM__
//! @brief Read current value of the ROM_COMPIDn_COMPID field.
#define BR_ROM_COMPIDn_COMPID(n) (BME_UBFX32(HW_ROM_COMPIDn_ADDR(n), BP_ROM_COMPIDn_COMPID, BS_ROM_COMPIDn_COMPID))
#endif
//@}

//-------------------------------------------------------------------------------------------
// hw_rom_t - module struct
//-------------------------------------------------------------------------------------------
/*!
 * @brief All ROM module registers.
 */
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
typedef struct _hw_rom
{
    __I hw_rom_entryn_t ENTRYn[3];         //!< [0x0] Entry
    __I hw_rom_tablemark_t TABLEMARK;      //!< [0xC] End of Table Marker Register
    uint8_t _reserved0[4028];
    __I hw_rom_sysaccess_t SYSACCESS;      //!< [0xFCC] System Access Register
    __I hw_rom_periphid4_t PERIPHID4;      //!< [0xFD0] Peripheral ID Register
    __I hw_rom_periphid5_t PERIPHID5;      //!< [0xFD4] Peripheral ID Register
    __I hw_rom_periphid6_t PERIPHID6;      //!< [0xFD8] Peripheral ID Register
    __I hw_rom_periphid7_t PERIPHID7;      //!< [0xFDC] Peripheral ID Register
    __I hw_rom_periphid0_t PERIPHID0;      //!< [0xFE0] Peripheral ID Register
    __I hw_rom_periphid1_t PERIPHID1;      //!< [0xFE4] Peripheral ID Register
    __I hw_rom_periphid2_t PERIPHID2;      //!< [0xFE8] Peripheral ID Register
    __I hw_rom_periphid3_t PERIPHID3;      //!< [0xFEC] Peripheral ID Register
    __I hw_rom_compidn_t COMPIDn[4];       //!< [0xFF0] Component ID Register
} hw_rom_t;
#pragma pack()

//! @brief Macro to access all ROM registers.
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
//!     use the '&' operator, like <code>&HW_ROM</code>.
#define HW_ROM         (*(hw_rom_t *) REGS_ROM_BASE)
#endif

#endif // __HW_ROM_REGISTERS_H__
// v22/130726/0.9
// EOF
